About
The Zfa extension provides several new instructions to improve the performance of floating point code for RISC-V. Of particular importance is the fli instruction for loading predefined constants into FP registers, but there are also fround instructions and additional comparisons/min/max instructions. The fli instructions will typically replace a load from the constant pool, so they're faster, smaller and reduce the data footprint of FP code as well.
https://github.com/a4lg/binutils-gdb/wiki/riscv_zfa
Stakeholders/Partners
RISE:
Ventana: Jeff Law. Oversight & Review
External:
Tsukasa OI authored the original binutils & gcc work – recently re-engaged
VRULL: Christoph Mullner has Tsukasa's work and has updated it per upstream review requests
Alibaba: Jin Ma has taken the mantle on Christoph's work
Dependencies
Status
Updates
- Minor bugfixes/enhancements to initial implementation landed. No known issues at this point
- Integrated Jin Ma's implementation plus some tests from Tsukasa's version
- Minor outstanding issue on whether or not zvfh implies zfh which will be addressed (if necessary) in a follow-up patch.
- Marking complete.
- Alibaba (Jin Ma) started pushing on it again
- Tsukasa has re-engaged as well with an implementation
- Tsukasa has indicated he prefers the Alibaba/VRULL implementation
- We'll look critically at both and try to pick the best overall implementation
- Updated binutils support posted, reviewed and integrated in time for binutils-2.41 branch
- QEMU posted and reviewed. Unsure of integration status
- Unblocks GCC work
- binutils/assembler work blocked on assembler documentation
- Note QEMU Zfa dependency
- Code review for assembler & compiler looks good
– Dates on or before June 15 are estimates
- Patches have been posted for both binutils and gcc. Realistically one issue remains to be resolved before both can move forward.
- Project reported as priority for 2H23