About

Enablement of auto-vectorization in LLVM for RISC-V, targeting the V extension version 1.0.   While the long term goal is to focus on vector length agnostic (VLA) approaches to vectorization, some of LLVM's vectorizer may still be biased towards fixed vector sizes.  Thus we expect to find cases that are not well handled using VLA approaches and we expect to support VLS approaches to vectorization a stop-gap alternatives.


LLVM's support for auto-vectorization on RISC-V appears to be improving regularly, but it is sensitive to having reasonable micro-architectural data available.  Thus it may be necessary to stub-out values for these key parameters when enabling auto-vectorization on a new micro-architecture, or to disable the costing model.

Stakeholders/Partners

RISE:

Ventana: 1 FTE focused on getting necessary uarch data ready

Ventana: 1 FTE Reference/target implementation of key x264 loops, breakdown of tasks that need to be solved to achieve desired code generation

SiFive: Craig Topper

Rivos:

External:

Alex Bradbury


Dependencies


Status

Development

COMPLETE


Development Timeline2H2023
Upstreaming

COMPLETE


Upstream Version

LLVM 17, Fall 2023

Will turn into llvm-17, fall 2023

Contacts

Jeff Law (Ventana)

Craig Topper (SiFive)


Dependencies




Updates

 

  • Basic functionality seems to be in place, splitting off further optimization work into a 1H2024 project

  • Evaluation of LLVM trunk indicates ongoing improvements for key routines in x264
  • Notable lack of strided memory accesses will impact x264 performance 

 

  • SLP (superword level parallelism or straight line parallelism) enabled for short vectors upstream
  • Ventana has lit up autovect in its internal LLVM tree after adding uarch details to that tree
    • One of the simpler routines now generating reference/target code

 

  • Project reported as priority for 2H23