About

This project aims to add the vector cryptographic extensions (0) in QEMU, adding crypto instructions that are aimed on Vector registers.

Adding this support will allow QEMU to be used as a hardware replacement for cryptographic development when hardware access with vector crypto support is not available.

(0) https://github.com/riscv/riscv-crypto/releases

Project Scope and Timelines

Changes to related files in target/riscv (for implementation of vector cryptographic extensions) and crypto & include/crypto & target/arm/tcg/crypto_helper.c (for sm4 related part) arounds:

• Refactor some of the generic vector functionality

• Share and reuse some cryptographic implementation (e.g. sm4, aes, etc.)
• Implement the vector cryptographic extensions
• Implement the disassembler of vector crypto instructions
• Implement Zvkt  & other shorthand extensions (e.g. Zvkn , Zvks , etc.)

Testing with the code samples provided by the vector cryptographic spec repository(ref.).

Components and Repos

Main repo: https://gitlab.com/qemu-project/qemu.git

Pending patch: https://lists.gnu.org/archive/html/qemu-riscv/2023-07/msg00289.html

Stakeholders and Partners

Dependencies

None

Measure of Success

Patch integrated.

1. v1.0.0-rc1 implementation (https://lists.gnu.org/archive/html/qemu-riscv/2023-07/msg00289.html)
   1. Zvkt  & shorthand extensions support (Will send other upstream patch set)
   2. Disassembler support (Will send other upstream patch set)

RISE Requirements

None

Misc info

The development was made by SiFive in collaboration with CodeThink.

Status