This project aims to add QEMU support for M and HS-mode virtual interrupt and IRQ filtering support, as described by the AIA specification (0), "5.3 Interrupt filtering and virtual interrupts for supervisor level" and "6.3.2 Virtual interrupts for VS level".

Enabling these 2 aspects of AIA in QEMU enables kernel developers to use QEMU to write drivers and user space software that supports AIA capable hardware. 

IRQ filtering is a use case of this change, i-e M-mode can stop delegating an interrupt to S-mode and instead enable it in MIE and receive those interrupts in M-mode and then selectively inject the interrupt using mvien and mvip CSRs.

Also, the spec doesn't mandate the interrupt to be actually supported in hardware. Which allows M/HS-mode to assert virtual interrupts to S/VS-mode that have no connection to any real interrupt events.

(0) https://github.com/riscv/riscv-aia

Project Scope and Timelines

Changes to target/riscv/{csr.c, cpu_helper.c} around:

  • Addition of mvien and mvip CSRs.
  • Addition of hvien CSR and updates in hvip CSR.
  • Changes into handling of sip, sie, vsip, vsie CSRs. (These can now have interrupts coming from virtual sources as well).
  • Changes into interrupt injection logic to account for virtual interrupts.

Note: hvip CSR previously was only used to inject VS interrupts. Also, those bit positions are present in mip CSRs as well as an alias. So QEMU implementation didn't use a separate hvip CSR variable and maintained those bits in mip. With hvip now being able to inject interrupts 13:63 (Virtual), and those are not same as mip 13:63 (hardware interrupts), we need to maintain those separately in hvip. So we have VS bits of hvip maintained in mip and 13:63 maintained in a separate hvip variable.

Components and Repos

Feature branch based on Upstream Qemu. https://github.com/rajnesh-kanwal/qemu/tree/dev/rkanwal/riscv_irq_filter_v2

Tested using hacking around Upstream Linux with AIA patches from Anup. https://github.com/rajnesh-kanwal/linux/commits/dev/rkanwal/aia_irq_filter

Tested using hacking around Upstream OpenSBI: https://github.com/rajnesh-kanwal/opensbi/commits/dev/rkanwal/irq_filter

Based on AIA spec: https://github.com/riscv/riscv-aia/releases

Stakeholders and Partners

Other target/riscv/{csr.c, cpu_helper.c} contributors as reported by get_maintainers.pl including:

  • Alistair Francis  
  • Weiwei Li   
  • Richard Henderson   
  • LIU Zhiwei   
  • Junqiang Wang  
  • Daniel Henrique Barboza  
  • Palmer Dabbelt  
  • Anup Patel  
  • Andrew Jones  
  • Philippe Mathieu-Daudé  
  • Bin Meng  
  • Atish Patra



Measure of Success

An accepted and tested design and implementation by end of 2H23.

RISE Requirements






Development Timeline






[PATCH v2 0/6] target/riscv: Add RISC-V Virtual IRQs and IRQ filtering support​

Upstream Version