Topic IDTopic NamePriorityDevelopmentUpstreamingDependencyTentative ETACompanyContactComments
Valgrind (00)
DP_00_001Valgrind vector supportHighInProgressInProgress
Q4 2023Intelfei2.wu@intel.com1. RV on Valgrind w/o Vector: https://github.com/petrpavlu/valgrind-riscv64
2. this task to support RVV framework + selected instructions on valgrind
DP_00_002Valgrind(mainly focus on the vector instruction support)MediumInProgressUnknown
?T-Headyunhai.syh@alibaba-inc.com
DP_00_003ValgrindLowUnknownUnknown
Q3 2023Ventanajlaw@ventanamicro.com

Basic rv64 functionality to run Linux binaries correctly. Then support for the extensions in RVA22/RVA23.

DP_00_004Valgrind bitmanip, V, Zvk, etc. supportMediumUnknownUnknown
2024SiFive

GDB (01)
DP_01_001GDBLowInProgressUnknown
 Q1 2024BOSCzhangjian@bosc.ac.cnHardware Watchpoints,Inferior function calls
DP_01_002Evaluate GDB status on RISC-VMediumUnknownUnknown

Andeshellosun@andestech.comhttps://wiki.riseproject.dev/pages/viewpage.action?pageId=395196
DP_01_003Add Zc support to GDB SimulatorMediumInProgressNotStarted
Q3 2023Imaginationsimon.harvey@imgtec.com

https://wiki.riseproject.dev/display/HOME/DP_01_003+-+GDB+Simulator+-+Add+Zc+support

LLDB (02)
DP_02_001LLDB for RV64LowUnknownUnknown

SiFivehttps://reviews.llvm.org/D62732https://reviews.llvm.org/D62732
DP_02_002Evaluate LLDB status on RISC-VMediumUnknownUnknown

Andeshellosun@andestech.comhttps://wiki.riseproject.dev/pages/viewpage.action?pageId=395196
gprofng (03)
DP_03_001gprof-ngLowUnknownUnknown
Q4 2023Ventanajlaw@ventanamicro.com

Basic support for RV, particularly as it moves into the datacenter. Probably not that important on the embedded side.

Perf (04)
DP_04_001Userspace Cycle/Instret accessHighCompletedDone
Q3 2023Rivos

Alexandre Ghiti <alexghiti@rivosinc.com>


DP_04_002Perf event discovery/encoding from json fileMediumDoneNotStarted
Q1 2024Rivosatishp@rivosinc.com
DP_04_003Perf CTR (equivalent of x86 LBR) supportMediumDoneNotStarted
Q1 2024Rivos, SiFive

atishp@rivosinc.com, eric.lin@sifive.com


DP_04_004Perf CTR call stack mode supportMediumUnknownUnknown
Q1 2024Rivos, SiFive

atishp@rivosinc.com, eric.lin@sifive.com


ASan (05)
DP_05_001Address sanitizerHighCompletedInProgress
2024T-Headyunhai.syh@alibaba-inc.comsupport RV32I in LLVM and GCC, research on optimization cooperate with Memory tagging extension
ToolChain (06)
DP_06_001riscv-gnu-toolchainUnknownUnknownUnknown

SiFivekito.cheng@sifive.com
DP_06_002binutilsUnknownUnknownUnknown

SiFivekito.cheng@sifive.com
DP_06_003ILP32 PSABIMediumInProgressUnknown
2024SiFivekito.cheng@sifive.com

PLCT guys has init implmenation, but need more survey for other ilp32 ABI like x32, ilp32/aarch64 and MIPS n32

DP_06_004DWARF representation for RVVUnknownUnknownUnknown

Red Hat

DynamoRIO (07)
DP_07_001DynamoRIOMediumInProgressCompleted
2024Rivosadlr@rivosinc.comWe kicked off the inital work and posted it upstream, but haven't been able to continue it
OpenLink (08)
DP_08_001openLink unifed debug probe protocol and firmwareMediumCompletedNotStarted
2024T-Headyunhai.syh@alibaba-inc.com
eBPF (09)
DP_09_001Evaluate status on RV: bpftraceMediumCompletedCompleted
2024T-Headcp0613@linux.alibaba.com

https://github.com/iovisor/bpftrace

The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.

DP_09_002Evaluate status on RV: bccMediumCompletedCompleted
2024T-Headcp0613@linux.alibaba.com

https://github.com/iovisor/bcc

The mainline already supports RV, we are already using it, please pay attention to enable kernel CONFIG.

DP_09_003Evaluate status on RV: ciliumUnknownUnknownUnknown




DP_09_004Evaluate status on RV: bpftuneUnknownUnknownUnknown




Performance Benchmarking and Analysis (10)
DP_10_001LKP framework enablement on RISC-VHighInProgressInProgress
2H2023Intelfei2.wu@intel.comhttps://github.com/intel/lkp-tests.git
DP_10_002LKP workload enablement on RISCV-VMediumInProgressInProgress
2024Intelfei2.wu@intel.com
Simpleperf
DP_11_001Simpleperf (primarily used on Android)HighUnknownNotStarted
1H2024SiFivekevin.mills@sifive.com
OpenOCD
DP_12_001Evaluate OpenOCD status on RISC-VUnknownUnknownUnknown

Andeshellosun@andestech.comhttps://wiki.riseproject.dev/pages/viewpage.action?pageId=395196





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